A general expression of dyadic Green's functions in radiallymultilayered chiral media

A general expression of spectral-domain dyadic Green's function (DGF) is presented for defining the electromagnetic radiation fields in spherically arbitrary multilayered and chiral media. Without any loss of the generality, each of the radial multilayers could be the chiral layer with different permittivity, permeability, and chirality admittance, while both distribution and location of current sources are assumed to be arbitrary. The DGF is composed of the unbounded DGF and the scattering DGF, based on the method of scattering superposition. The scattering DGF in each layer is constructed in terms of the modified and normalized spherical vector wave functions. The coefficients of the scattering DGFs are derived and expressed in terms of the equivalent reflection and transmission coefficients, by applying boundary conditions satisfied by the coefficient matrices     

Many strings attached: from conventional to robotic marionette manipulation

This paper introduces the evolution of traditional marionette design and manipulation skills from an engineering perspective and describes a novel system developed in Nanyang Technological University, called Robotic Marionette Systems (ROMS). Through the development of ROMS and the marionette motion generation methods, the possibility of infusing modern robotic and mechatronic technology into the traditional art form of marionette performance is explored while, at the same time, evoking and stimulating public interests in this art form.     

Electrical and optical activation studies of Si-implanted GaN

Comprehensive and systematic electrical and optical activation studies of Si-implanted GaN were made as a function of ion dose and anneal temperature. Silicon ions were implanted at 200 keV with doses ranging from 1×10¹³ cm^?2 to 5×10¹⁵ cm^?2 at room temperature. The samples were proximity-cap annealed from 1050°C to 1350°C with a 500-Å-thick AlN cap in a nitrogen environment. The optimum anneal temperature for high dose implanted samples is approximately 1350°C, exhibiting nearly 100% electrical activation efficiency. For low dose (≤5×10¹⁴ cm^?2) samples, the electrical activation efficiencies continue to increase with an anneal temperature through 1350°C. Consistent with the electrical results, the photoluminescence (PL) measurements show excellent implantation damage recovery after annealing the samples at 1350°C for 20 sec, exhibiting a sharp neutral-donor-bound exciton peak along with a sharp donor-acceptor pair peak. The mobilities increase with anneal temperature, and the highest mobility obtained is 250 cm²/Vs. The results also indicate that the AlN cap protected the implanted GaN layer during high-temperature annealing without creating significant anneal-induced damage.     

1 V 10 GHz CMOS frequency divider with low power consumption

A low supply voltage and low power ultra-high frequency divider is investigated. The proposed inverter of the frequency divider is able to operate at higher frequencies with enhanced output voltage swing and lower power consumption under an ultra-low supply voltage compared to that of existing divide-by-2 units. The frequency divider implemented with this inverter using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 10 GHz for a 1 V supply voltage with 1.3 mW power consumption.     

Cost-tolerance relationships for non-traditional machining processes

In recent years, non-traditional machining processes have been growing in popularity and their applications have continued to increase. However, very limited research work has been carried out to investigate their economic implications on tolerance allocation. This paper reports on cost-tolerance relationships for non-traditional processes, namely, electrical discharge wire machining and laser beam machining. Medium carbon steel plates are machined using the two processes to obtain cost-tolerance data which are fitted to various mathematical models. A third-degree polynomial function has been found which gives the most representative fit to the data obtained. An example is presented to illustrate the application and to compare the cost implication of the two machining processes.     

Carrier backscattering characteristics of strained silicon-on-insulator n-MOSFETs featuring silicon–carbon source/drain regions

This work investigates for the first time, the physics of carrier transport in a sub-90 nm strained silicon-on-insulator (SOI) n-MOSFET with silicon–carbon (Si:C) source/drain (S/D) regions. The insertion of Si:C in the S/D exerts a lateral tensile strain in the transistor channel, leading to appreciable drive current enhancement. Significant improvement in both carrier backscattering r_sat and source injection velocity υ_inj were observed, accounting for the large drive current I_Dsat enhancement in Si:C S/D transistors. This improvement becomes more appreciable as the gate length is reduced. The reduction in r_sat is related to a shorter critical length ℓ₀ for carrier backscattering. On the other hand, the splitting of six-fold degenerate conduction band valleys due to strain-induced effects results in a reduced in-plane transport mass and thus contributes to significant υ_inj enhancement. In addition, the dependence of drive current performance on source injection velocity and ballistic efficiency in a short channel MOSFET is also discussed.     

A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors

Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.